Hardware Timed Send
Starting from version 2.4, KPA EtherCAT Master begins supporting Hardware timed send feature. This feature enables sending of cyclic EtherCAT frames precisely at the beginning of the Master cycle. Usually, the Master starts assembling the frame at the beginning of its cycle, therefore, the actual time of transmission is delayed by the preparation.
The hardware-timed send feature can only be activated if the target system has a hardware timer. With hardware-controlled sending enabled, the Master prepares the frames in advance before starting the cycle and transfers them to a hardware module (HW module) on the target. Therefore, when the cycle starts, the HW module just sends the prepared frames without delay. The function is applicable for target systems developed based on the Xilinx Zynq SoC / Zynq UltraScale+ MPSoC family, Intel FPGA Cyclone V SoC and Texas Instruments Sitara AM437x/AM57x. The function is licensed as an additional product feature.
Emulation of Timed Send
If the target system does not include a hardware timer, the hardware timed send function cannot be enabled, but a software emulation of it can be used. Timed send emulation makes it possible to mimic the timed send functionality. Both the emulation and the hardware-assisted timed send minimize jitter when sending cyclic frames.
Similar to the hardware-assisted operation, in emulation, Master also assembles frames before the cycle start, therefore, it sends the frame as soon as the cycle begins.
This feature is included in all Master classes and requires no additional licensing.
Using a hardware module allows achieving higher accuracy in sending of frames, less then 1 µs. This feature uses a scheduler for sending the frames, hence it speeds up the process of sending as well.
The timed send emulation is a software solution so it does not offer the benefits of HW module (accuracy and sending speed). The timed send emulation intends to provide the same control interface as the hardware timed send functionality. Its interface allows to build cyclic frames in advance (automatically or by user request) and to schedule a send request to the driver. But as a software nature of the timed send emulation it can jitter due to an operation system dependent timer jitter, while the hardware timed send does not have a jitter because of using hardware timer interrupts.